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Look at files for instructions. researching your topics and reading through conference/journal papers – Literature search/review of conference and journal papers on selected topics – Need at least 2 conference and 2 journal papers cites in your review papers – Journal papers can not be briefs – Sources for material: IEEE Xplore (primary), Web of Science (or other search database).
3-D IC Multi-Plane Synchronization TechniquesDepartment of Electrical and Computer Engineering, Drexel University, Philadelphia, Pennsylvania 19104Abstract—Clock distribution and synchronization is a deeplyanalysed and mature field in 2-D Integrated Circuit (IC) design.Vertical integration of heterogeneous 2-D ICs using throughsilicon vias (TSV) has introduced new challenges in achievingsynchronization in clock domains spread across multiple deviceplanes in a 3-D IC stack. This survey paper explores the currentstatus of research in the area of multi plane synchronization in3-D ICs.I. INTRODUCTIONClock signals are the fundamental control signals in anysynchronous digital system. The correct operation of the digitalsystem is dependent upon the precise temporal reference providedby the clock signals which traverse the largest distanceacross the chip and have the highest fanout. Technologyscaling deteriorate the performance of clock signals as shrinkingwidths of global interconnects increases the resistance[1]. Over the years, considerable research has been done tooptimize clock signal generation and distribution across a 2-D chip ensuring clock skew between sequentially-adjacentpairs of registers does not exceed roughly one-tenth of themaximum clock frequency. With the emergence of TSV based3-D IC technology, a new dimension has been added to theclock distribution network. The goal is to achieve multi-planesynchronization with minimal power and area overhead. Thispaper addresses the timing complexity introduced by 3-D ICs,the modelling of the clock distribution network and the impactof process variation on the timing of the clock signal fordifferent die stack configurations. The paper is organized asfollows: Section II provides an overview of clock distributionnetworks in 2-D ICs. Research towards optimizing clockdistribution networks in 3-D ICs is summarized in SectionIII. Subsections describing the clock distribution models, clockskew optimization techniques, and impact of process variationon clock skew are provided. Multiple research papers areanalysed and potential concerns in the methodology adoptedare discussed. Future research in achieving multi-plane clocksynchronization is proposed in Section IV. Concluding remarksare provided in Section V.II. CLOCK DISTRIBUTION NETWORKS IN 2-DINTEGRATED CIRCUITSSeveral clock distribution techniques for synchronous circuitshave been developed [1], [2] for equipotential clockdistribution across a 2-D IC. Symmetric interconnect structureslike H-trees and X-trees are popular implementations. Othercommonly used grid like implementations are ring and meshes.Asymmetric structures such as buffered trees and serpentinesThis literature survey is done as part of course requirement for ECEC-690:Custom VLSI and Analysis, Winter 2014. Figures included in this paper aresourced from the technical papers cited.[3] are also used.A synchronous system with an optimized clock distributionnetwork design performs better than an asynchronous system.The circuit reliability is ensured by controlling the clock skewrather than clock delay. A precise range within which theclock skew for each local data path must fall is defined in[1]. Symmetric clock tree topologies adapt well to enforce theclock skew to fall within this range. Sophisticated tools existfor automated synthesis of 2-D IC clock distribution networkswhich also take into account effect of process variation thusyielding process insensitive clock distribution networks. It is amatter of time for such tools to be available for 3-D ICs oncethe clock skew variations introduced by the third dimensionalong with constraints imposed by physical properties ofmaterials used in the 3-D stack are well understood.III. CLOCK DISTRIBUTION NETWORKS IN 3-DINTEGRATED CIRCUITSDesigning a clock distribution network for a 3-D ICadds additional parameters in the decision matrix at both thearchitectural and circuit levels. The primary motivation tomove towards TSV based vertical integration of 2-D ICs is tominimize the length of global interconnects. 3-D integrationfacilitates faster operation with a smaller footprint at the costof higher power density. The floor plan of each die and stackconfiguration are two important parameters which can impactthe maximum frequency of operation, power consumption, andsystem reliability. The positioning of dies in the stack is influencedby the power delivery network and clock distributionnetwork. It is highly probable that the sequential elementsdriven by the same clock source are placed on different planes.The positioning of the clock source to ensure delivery of theclock signal with zero skew to two sequentially adjacent pairof registers located on disparate plans is a challenging task.Modifications required to conventional 2-D clock distributionnetworks to achieve synchronization in 3-D ICs are describedin Section III-A. Clock distribution models for 3D ICs aredescribed in Section III-B. The impact of inter die and intra dieprocess variations on multi-plane synchronization is describedin Section III-C.A. 3-D Clock network topologiesConsider three dies in a 3-D stack with the central diecontaining the clock driver. The clock signal is distributedthrough H-trees locally within each die. As shown in Fig.1-a[4], the signal propagation in the vertical direction is througha TSV (shown as dotted line) which produces a differentimpedance profile as compared to the interconnect propagatingthe clock signal within the plane.Fig. 1. Three different clock distribution network for 3-D IC: (a) H-trees,(b) H-tree and local rings, (c) H-tree and global rings [4].The design of symmetric interconnect structures like theH-tree require an account of the TSV electrical characteristics.The placement of the clock driver is such that the clocksignal traverses identical vertical interconnect paths. Identicalpaths are possible if the clock driver (root) is placed in a planewhich is equidistant from the planes where the clock signal willsink (leaf). For stack configurations preventing such geometricsymmetry, the delay difference due to a shorter signal path ina given direction is compensated by placing fewer TSVs (thusoffering higher impedance) between two adjacent planes.A logical step is to extend the same topologies on differentplanes of the 3-D stack from the topologies developed for2-D IC symmetric clock distribution, while including frequencydependent delay and skew produced by the TSVs.The authors in [4] study three clock topologies as shown inFig.1. The three test circuits with different clock topologiesare fabricated by MIT Lincoln Laboratory (MITLL) witha fully depleted silicon-on-insulator (FDSOI) 3-D processand tested to measure the clock skew, delay, slew rate, andpower consumption. Each device plane contains identical logiccircuit. It is confirmed through measurements on the fabricatedcircuits that the clock network topology in Fig. 1(a) (H-treesin each plane) offers the lowest clock skew and highest powerconsumption. The clock topology in Fig. 1(b) (H-tree in centralplane and local rings in planes 1 and 3) offers the highestclock skew and lowest power consumption. The high clockskew in this configuration is attributed to the large numberof TSVs used. The measured root to leaf clock delay is thelargest for the clock network configuration shown in Fig. 1(c)(H-tree in central plane and global rings in planes 1 and 3).The experiments bolster the theoretical understanding that theposition and number of TSVs along with the clock topologyadopted in each plane influence the global as well as localclock skew and delay. A trade-off needs to be made betweenpower consumption and clock signal quality while choosing anappropriate clock network topology for each plane. The clockdelay is a parameter of lesser importance than clock skew whenmaking decisions for optimum clock network topology.The experimental results presented in [4] indicate that a clearcorrelation between the inter-plane clock skew and clockfrequency is not established. Developing a relationship modelbetween the maximum clock skew and operating frequency fora given clock distribution topology (fixed number and positionof the TSVs) is beneficial to approximate inter-plane clockskew for different technology nodes. Importance of such arelationship model is increased due to the fact that clock skewbudget reduces with increase in clock frequency. No publishedwork exists which studies this interdependence.Existing electrical models to estimate clock delay from root toleaf in 2-D ICs can be extended to estimate the clock delayin a 3-D IC stack. The next section describes the work donetowards developing such electrical models.B. Clock distribution modelling for 3-D ICsAnalysis of the experimental results obtained in [4] suggestthat accurate modelling of clock distribution networksspanning multiple device planes in 3-D ICs is required sothat right clock distribution topology can be chosen earlyin the design phase. In [5], the experimental results of rootto leaf delays for the three clock distribution networks (Fig.1) in [4] are compared with the root to leaf clock delaysobtained by using equivalent electrical models for each clockdistribution network. The TSVs are modelled using the closedform expressions for resistance, inductance and capacitancedeveloped by the author in [5]. Fig.2 [5] shows the structureand equivalent electrical model of the TSV. The electricalparameters incorporated in numerical simulations to model theinterconnect segments within a plane of the clock networkinclude DC self and mutual inductance, asymptotic self andmutual inductance, DC resistance, 1 GHz resistance, and trendlines for the capacitance. Two ground return paths spaced 2m apart on either side of the clock line are used to provideaccurate estimate of the capacitance. The electrical path ofthe clock signal propagating from the root to leaf is dividedinto 50 m segments with each segment represented as a –network. Fig. 3 [5] illustrates the electrical path of the clocksignals propagating from root to leaves in each plane of theH-tree topology shown in Fig. 1(a). The number of parallelTSVs between device planes is shown inside the ovals in Fig.2.Fig. 2. Structure of TSV and equivalent electrical model [5].The remaining two clock network topologies using localand global rings are modelled similarly, the difference beingthat for local ring topology (Fig. 1(b)) the clock signal isdistributed to planes A and C from the leaves of the H-tree inplane B where as for global ring topology (Fig. 1(c)) the clocksignals to planes A and C is sourced from buffers at level-2 ofthe four level H-tree in plane B. The interconnect connectingthe leaf to the output pad is also modelled as a -networkwith varying lengths (0 to 150 m) depending upon the clocktopology.The modelled clock delay for all three configurations showsless than 10% error for all clock paths within a specific clocktopology barring one anomaly in plane A for local ring topology.The accuracy between modelled and experimental clockFig. 3. Structure of clock path from Fig. 1(a) used for modelling clock delay [5].delays for all three circuit topologies proves that the closedform expression of the TSV electrical parameters developedfor the MITLL FDSOI 3-D process provide good estimate ofthe TSV impedance in the fabricated test circuit. The closedform expressions for the resistance, inductance and capacitancecan thus be integrated into physical synthesis tools along withTSV placement information to model the clock delay andclock skew across disparate device planes operating at subgigahertzfrequencies. However, there are certain limitationsin the electrical model developed for 3-D IC clock networkanalysis.The closed form expressions developed in [5] forTSV electrical parameters do not take into account impact ofphysical parameters like temperature and mechanical stress onTSV and are valid only for sub-gigahertz frequencies. Theclock skew measured on the three planes of the fabricated testcircuit in [4] is not compared with the clock skew obtained byusing the electrical model for TSV and interconnects in [5].As clock skew variation is of higher concern than clock delay,the accuracy of the electrical model cannot be confirmed.The electrical parameters of the TSV vary non-linearly withtemperature and mechanical stress induced in the TSV. Thesevariations can lead to unpredictable clock delay and skewacross multiple planes, thus a TSV physical model includingthe non-linear dependence on temperature and mechanicalstress needs to be developed. In [6], an electrical-thermalmechanicaldelay model is developed for 3-D IC clock distributionnetwork. Reduction in thermal and mechanical stressgradient with strategic insertion of dummy TSVs (TSVs notpropagating any electrical signal) is achieved. Fig. 4 showsclock delay reduction with dummy TSV insertion. An averagereduction of 61% in clock skew is possible by using the nonlinearelectrical-thermal-mechanical delay model developed in[6].C. Impact of process variation on 3-D IC clock distributionnetworksIntra-die process variability is well studied for 2-D ICs anddesign techniques have been proposed to make clock networksinsensitive to process variations [1]. 3-D ICs introduce inter-dieprocess variation and the impact on clock network performancerequires detailed analysis. The authors in [7] study the skewvariation across multiple clock domains and the impact ofspatially correlated process variations on 3-D clock trees.Fig. 4. Clock-skew reduction and distribution before and after insertion ofdummy TSVs [6].The clock skew variation with process variation analysis isperformed on four different configurations. First configurationhas one clock domain per plane. The second configurationhas two clock domains per plane each spanning four planes.The third configuration is shown in Fig.5(b) with four clockdomains per plane with each domain spanning two planes. Thefourth configuration is shown in Fig.5(a), with four differentclock drivers implementing four clock domains placed onthe lowest plane and the four clock trees span the fourplanes through TSVs. Simulation to measure clock skew perclock domain for each configuration is performed. Two casesare considered, uncorrelated within-die process variations andmulti-level correlations of within-die process variations. Fromthe simulated results, two guidelines are formulated. The firstguideline states that for uncorrelated within-die process variations,extending the span of a clock domain to multiple planesreduces maximum skew variation but may not necessarilyproduce smallest skew variation if the span is increased tomaximum supported planes. The second guideline states thatfor multi-level within-die process variations, the skew variationincreases as the number of planes the clock domain spansincreases. The maximum skew variation being dependent ondie-to-die and within-die variations.A Hybrid H-tree topology with careful partitioning of thecircuit to decrease the pair-wise skew variation within a 3-D IC is proposed in [8]. Registers which store data in acommon datapath when placed on different planes driven byFig. 5. Clock domain configuration used to study multi plane clock skewwith process variation. (a) Four Clock domains within each plane (b) Twoclock domains within each plane [7].an independent H-tree, show reduction in skew variability.This fact is beneficial for applying techniques for clock skewreduction at behavioural synthesis stage. The analysis of interand intra-die process variation on 3-D ICs in [7] and [8] showthat intra-die variations affect the devices placed on one planeunequally thus it is possible to reduce the impact of processvariations as compared to 2-D ICs.IV. FUTURE AREAS OF WORKPower supply noise due to dynamic switching of devicesin different planes of a 3-D IC can have deleterious effecton the clock jitter. Process variations will further exacerbatethe clock skew. Hence, it is important to study the combinedeffect of dynamic power supply noise and process variationson clock skew and jitter. Such an analysis is performed in[9]. The combined model developed is used to study thevariation of clock jitter and skew across 3-D IC stack. However,the analysis falls short in studying only the periodicjitter introduced in clock signals due to power supply noise.The analysis can be extended to include the impact on otherdeterministic (inter symbol interference on data lines) andrandom jitter (thermal and shot noise) components. Finally, acomposite analytical model needs to be developed which takesinto account electrical,thermal and mechanical characteristicsof TSVs (as done in [6]) along with power supply and processvariation (as done in [9]) to achieve the best 3-D IC clock treesynthesis technique.V. CONCLUSIONSAchieving clock synchronization across multiple planesin a 3-D IC is a challenging task involving simultaneousanalysis of multiple parameters such as clock domain configurationacross planes, TSV location, TSV physical modellingincluding thermal and mechanical stress, inter-die and intradieprocess variation. 3-D IC clock tree synthesis techniquesefficiently model the technology dependent TSV parameters,showing good correlation with experimental data. Existingsymmetric clock distribution network topologies used in 2-DICs may not yield efficient results in a 3-D configuration if theclock domain assignment across planes is not carefully plannedincluding the impact of inter and intra-die variations. Includingthe non-linear electrical-thermal-mechanical delay model inclock tree design can result in significant reduction in clockskew. Dynamic power supply noise and process variationswhen modelled together can help better optimize clock jitterand skew. Further work is needed to model process and powersupply variation with different clock domain configurations.REFERENCES[1] Eby G Friedman, “Clock distribution networks in synchronous digitalintegrated circuits,” Proceedings of the IEEE, Vol. 89, No. 5, pp. 665–692, May 2001.[2] Thucydides Xanthopoulos, Clocking in Modern VLSI Systems, Springer,2009.[3] Emre Salman and Eby G Friedman, High Performance Integrated CircuitDesign, Mc Graw Hill, 2012.[4] Vasilis F Pavlidis, Ioannis Savidis, and Eby G Friedman, “Clockdistribution networks in 3-D integrated systems,” IEEE Transactionson Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 12, pp.2256–2266, December 2011.[5] Ioannis Savidis, Vasilis Pavlidis, and Eby G Friedman, “Clock distributionmodels of 3-D integrated systems,” IEEE International Symposiumon Circuits and Systems (ISCAS). IEEE, pp. 2225–2228, May 2011.[6] MPD Sai, Hao Yu, Yang Shang, Chuan Seng Tan, and Sung Kyu Lim,“Reliable 3-D Clock-Tree Synthesis Considering Nonlinear CapacitiveTSV Model With Electrical–Thermal–Mechanical Coupling,” IEEETransactions on Computer-Aided Design of Integrated Circuits andSystems, Vol. 32, No. 11, pp. 1734–1747, November 2013.[7] Hu Xu, Vasilis F Pavlidis, and Giovanni De Micheli, “Skew variabilityin 3-D ICs with multiple clock domains,” IEEE International Symposiumon Circuits and Systems (ISCAS). IEEE, pp. 2221–2224, May 2011.[8] Vasilis F Pavlidis, Hu Xu, Ioannis Tsioutsios, and Giovanni De Micheli,“Synchronization and power integrity issues in 3-D ICs,” IEEE AsiaPacific Conference on Circuits and Systems (APCCAS). IEEE, pp. 536–539, December 2010.[9] Hu Xu, Vasilis F Pavlidis, Xifan Tang, Wayne Burleson, and GiovanniDe Micheli, “Timing Uncertainty in 3-D Clock Trees Due to ProcessVariations and Power Supply Noise,” IEEE Transactions on Very LargeScale Integration (VLSI) Systems, pp. 2226–2239, December 2013.
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